<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"><channel><title>Netvouz / simoncov / tag / unisim</title>
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<description>simoncov&#39;s bookmarks tagged &quot;unisim&quot; on Netvouz</description>
<item><title>ModelSim</title>
<link>http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=1923&amp;BV_SessionID=@@@@1317946424.1185098532@@@@&amp;BV_EngineID=cccgaddlgidjdlmcefeceihdffhdfjf.0</link>
<description>How do I compile the UniSim, and CORE Generator HDL libraries?</description>
<category domain="http://netvouz.com/simoncov?category=2626452500730634539">HW &gt; FPGA</category>
<author>simoncov</author>
<pubDate>Thu, 13 Sep 2007 17:28:45 GMT</pubDate>
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